The present invention relates generally to chip carriers and printed circuit boards, and deals more particularly with a method for fabricating chip carriers and printed circuit boards.
Printed circuit boards (PCBs) are well known and comprise multiple layers of dielectric material with metallizations on the layers. The metallizations comprises conductors, power planes, ground planes, internal pads and surface lands. The metallizations are used to connect the components to each other and to I/O pads and provide power and ground. Typically, electronic components are mounted on the exposed surface of at least one of the surface layers. Because the surface layer cannot always accommodate all the requisite conductors, the metallizations on the inner layers are used to provide many of the interconnections. Plated through holes (PTHs) are commonly used to interconnect conductors on different layers. A PTH comprises a metal pad on each of the layers to be interconnected, a hole passing within the metal pads through all the layers, and copper plating on the inner surface of the hole to interconnect the two pads. Pads within the PCB are connected by conductors as required. An electronic component may be soldered to a "surface land") of the final printed circuit board, and the surface land may be connected to an inner layer by a PTH.
A problem with the foregoing technique is that some types of solder and flux, when reflowed i.e. melted, to join the electronic component to the surface land, flow entirely through the PTH and may inadvertently contaminate a layer on the opposite side of the printed circuit board. While there are some solutions to this problem--use of high metal alloy solder balls that do not flow so readily, use of large surface lands which receive solder away from the PTH and use of solid surface lands that cover the PTH, all these solutions significantly add to the cost or size of the resultant product.
A chip carrier may comprise a thin film substrate such as metallized polyimide and be used to mount an integrated circuit for connection to other components and I/O. Metallizations are also provided on both surfaces of the chip carrier, and typically comprise surface lands and conductors. A PTH is also utilized to make an electrical connection between the metallizations on the two surfaces. A chip lead may be soldered to a surface land associated with the PTH or to a conductor leading to the surface land. If the chip lead is soldered directly to the surface land, the same problem may occur in that some types of solder and flux, when reflowed to join the chip lead to the surface land, flow entirely through the PTH and may inadvertently contaminate the metallizations on the opposite surface. While the same types of solutions as described above are possible, they are not cost effective or utilize too much surface area.
The chip carrier may be attached to a printed circuit board as follows. A solder ball is attached to the surface land on the opposite surface as that which mounts the chip. Then, the PCB is positioned beneath the chip carrier such that the solder ball contacts a surface land of the PCB. Then, the solder ball is reflowed to connect the surface land of the chip carrier to the surface land of the PCB. The same problem as described above may occur in that some types of solder and flux, when reflowed to join the surface land of the chip carrier to the surface land of the PCB, flow entirely through the PTH of the PCB and may inadvertently contaminate the metallizations on the opposite surface of the PCB. While the same types of solutions as described above are possible, they are not cost effective or utilize too much surface area.
Accordingly, a general object of the present invention is to provide a cost effective method for soldering electronic components to printed circuit boards and chip carriers with PTHs and soldering chip carriers to PCBs such that solder and flux do not inadvertently flow entirely through any of the associated PTHs.